2.5D 와 3D 반도체 패키징의 진화

Semiconductor packaging has progressed from 1D PCB levels to cutting-edge 3D hybrid bonding at the wafer level, achieving single micronmeter level interconnecting pitches and over 1000 GB/s bandwidth. Key parameters include Power, Performance, Area, and Cost. Power efficiency improves through innovative packaging, while Performance benefits from shortened interconnection pitches. Area requirements vary for high-performance chips and 3D integration's smaller z-form factor. Cost reduction involves material alternatives and enhanced manufacturing efficiency. In 2.5D, interposers include Si-based, organic-based, and glass-based options. In 3D, microbump technology evolves for smaller pitches, with the current single-digit micronmeter pitch achieved through hybrid bonding, a groundbreaking Cu-Cu connection method.

 

In this webinar, Senior Technology Analyst Dr. Yu-Han Chang will present IDTechEx's latest research findings for the advanced semiconductor packaging industry, which will include research from IDTechEx's new market research report: "Advanced Semiconductor Packaging 2024-2034: Forecasts, Technologies, Applications".

 

This webinar will reveal insights into 2.5D and 3D advanced semiconductor packaging technologies and the content include: